| 摘要 |
PURPOSE:To realize high speed and high density of ROM, by preventing accumulation of parasitic capacitances of a plurality of sense lines, through the connection of the sense line only selected with the switch controlled with the column line, to the sense common bus. CONSTITUTION:The gate electrode of memory element M4111,... of MOSFET is connected to the row lines r41,..., and the source and drain are respectively connected to the column lines C41,... and sense line S41,... when the address information is at ''1'', and no connection is made at the information ''0''. Further, C41 only is selected to low level at the column address circuit 4 and r41 only is selected to high level at the row address circuit 2, then, MOSFET-M4111 and M4112 are slected and the sence common buses SB41, SB42 are made to low level through the switch FETQ41, Q42 controlled with the sense lines S41, S42 and the column line C41. |
