| 摘要 |
PURPOSE:To generate a square wave train with a phase precision lower than the access time of storage circuits by supplying phase data to plural storage circuits at intervals of a time longer than the access time of storage circuits and converting individual stored data to time series data and transmitting them. CONSTITUTION:A pulse train from a clock source 4 is led to a counter 2 through frequency dividing circuits 13 and 14, and the counted value is supplied to ROMs 161-164 successively. In each of ROMs 161-164, phase data at intervals of 1/16 period of a 1MHz signal are stored in individual addresses in order. ROMs 161-164 have data outputs 01-08 in accordance with square wave trains led to mixing circuits MX1-MX8, and outputs 01-08 are transmitted to a bus 19 through latch circuits 171-174. Data selectors 151-158 take in data on the bus 19 and convert data to time series data and transmit them. |
