| 摘要 |
The memory element, compatible with polycrystalline silicon gate CMOS technology, includes a single p-channel transistor (TM) with floating gate (G1) arranged opposite a control electrode (G2). The erasure of this element is performed by electron-field emission from the floating gate (G1) to the substrate (G1) and the writing by avalanche into the p<+>n junction of the drain (2), in such a way that the transistor is never conducting at zero control voltage, whether the element be written to or erased. This memory element is reprogrammable by means of voltages produced from the supply voltage provided by a battery, by circuits fully integrated on the same board as the memory. It can be used particularly advantageously in a matrix arrangement. <IMAGE> |
