| 摘要 |
PURPOSE:To realize a high-speed division with an extremely small error for the system in which a division is carried out via a high-speed multiplying device, by performing the conversion of the binary divisor and a division with no successive repetition by the division of the conversion number. CONSTITUTION:The system comprises with the fundamental constitution using the divisor conversion read-only memories 4-6, the multiplying devices 1-3 plus adder rows 7-7; and these component units are coupled in a single direction to secure an asynchronous working. In this case, the conversion number of the Nh digits corresponding to the divisor of the h digits in 1:1 is used and then grouped into the division numbers in the order of the higher-rank digits, and then three units of the division number are delivered from the memories 4-6. This output is suppllied to one side of the devices 1-3, and the dividend is supplied to the other side of the devices 1-3 each to obtain the output of the 2h digits at the output. This output is grouped again into the division product of the upper and lower digits, and the upper and lower division products of the two different multiplying devices to form a facies are applied to the row of adders 8-10 to which the carry output/input line is connected. Thus a division is carried out with the conversion of the binary divisor with no successive repetition by the division of the conversion number. Then a high-speed division is possible with an extremely small error. |
