| 摘要 |
PURPOSE:To make it possible to transfer the output of the 1st logic element to the 2nd logic element without delay, by interposing a ratio type logic element between the 1st and 2nd ratioless logic elements driven by a clock pulse. CONSTITUTION:Between NOR gate 19 and NAND gate 21 driven by clock pulse phi1, ratio type inverter 20 is connected which is not driven by the clock pulse. To one input terminal of NOR gate 19, input signal (d) of logic [1] is supplied and to the other input terminal, input signal (e) of logic [0] is supplied, so that an output signal of logic [0] will be led out of NOR gate 19 at the rise of clock pulse phi1. This output is inverted by inverter 20 without phase delay to obtain an output signal of logic [1]. Consequently, the output signals with no delay between the output of NOR gate 19 and that of NAND gate 21 can be sent out. |
