| 摘要 |
PURPOSE:To obtain a time-division switching network of high reliability by reducing the amount of hardware and electric power consumption by combining a low- speed memory, low-speed logic circuit, minimum high-speed memory, and high- speed logic circuit. CONSTITUTION:Channels on the 1st and l-th time-division digital common lines 31 and 36 are converted by low-speed memory switch circuits 32 and 37 into channel phases, which are applied to time-division multiplexing circuit 41. Then, circuit 41 converts the input into single high-speed time-division digital common line 42 of N=nxl in multiplicity and in high-speed memory switch circuit 43, the circuit that corresponds to the speed of common line 42 makes N channels into a set of (m) continuous channels. Then, the output of this common line 46 is converted again by time-division multiplex separating circuit 47 into l time-division digital common lines 48 and 53 of (n) in multiplicity, which are further converted by low- speed channel memories 50 and 55, reducing the amount of hardware and electric power consumption. |
