| 摘要 |
PURPOSE:To obtain the features of an SOS architecture in the MOS inverter while forming a bulk MOS architecture by limiting the elongation of a depletion layer from the drain of a driver MOS transistor by the depletion layer from the substrate, thereby reducing a parasitic capacity caused by the P-N juction at the output terminal. CONSTITUTION:A P<-> type layer 2 is epitaxially grown on an N<-> type Si substrate 1, a shallow N<+> type source region 4 and a deep N<+> type drain region 5 are diffused on an interval therein, and the interval between the bottom of the region 5 and the substrate 1 is thus sufficiently reduced. Then, a shallow N<-> type region 8 is diffused while disposing itself outside the region 5 by making contact with the region 5, and a gate insulating film 6 is coated on the exposed layer 2 between the regions 4 and 5, and a gate electrode 7 is coated thereon. Thereafter, the layer 2 is mesa etched at the periphery, and is buried with a thick SiO2 film 3 reaching the substrate 1, the regions 4, 5 are used for the drive MOS transistor Q, and the region 8 side is used as a load R operating similarly to the junction type FET. |
