| 摘要 |
PURPOSE:To make it possible to reduce the cost by using inexpensive elements when providing a circuit to every line by increasing an arithmetic speed by performing arithmetic of every bit string, unitized to a fixed length, simultaneously in frame transmission and reception. CONSTITUTION:When a bit string of a fixed length arranged in parallel on a transmission line arrives, continuous-[1]-pattern detecting circuit 1 finds the number of continuous [1]s from the head and tail of the bit string. On the basis of this number and that of continuous [1]s right before the arrival bit string stored in memory 3, pattern detecting circuit 4 detects various patterns and, on flag detection, sends out information F on the flag position of the arrival bit string. On aport, idle detection, pieces of information A and I are sent out. Zero-deleting circuit 5 detects [0] inserted for transmissivity and performs deletion. Then, parallel shifter 10 extracts a bit string of the fixed length newly and CRC arithmetic circuit 11 processes the constant-length bit string in parallel as it is. |
