摘要 |
<p>The analog sample data filter in integrated circuit form has a capacitor (C1) which is periodically brought into operation and out again during successive timing cycles connected by a set of capacitors (C2,C3,Cn) in series to an integrating capacitor (5). In parallel with each series capacitor is a switching device which is closed during the first timing phase. The first capacitor, which is connected intermittently, has the same capacity as the series capacitors and the integrating capacitor has a capacitance given by a constant which includes the number of the series capacitors. The first capacitor is controlled by a differentiating input voltage during the first timing phase.</p> |