| 摘要 |
A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication channel device are processed under the control of the adapter firmware to effectuate CRC checking, byte size control, extended and variable field format control, partial last byte control, and block transfer control functions on the transmitted/received data stream. First-in-first-out (FIFO) buffer memories are employed in the transmit circuits to queue a frame of transmit data and control characters at the adapter whereby the communication processor/adapter interface control is simplified. Similarly, a FIFO buffer is employed in the receive circuits to reduce the frequency of receive interrupts and to enable block transfer of received data to the processor. |
