OVERLAP PCM CODER/DECODER WITH REACTION TIME COMPENSATION

摘要

OVERLAP PCM CODER/DECODER WITH REACTION TIME COMPENSATION A PCM coder/decoder circuit is disclosed employing a counter that counts clock pulses until a transmitting ramp voltage equals that of an outgoing speech sample. The encoded count is transmitted in complemented form to the distant station where it is eventually entered into a counter similar to that of the transmitting station. Clock pulses are then applied to the receiving counter until a carry is generated at which time a receiving ramp waveform is disconnected from a decoding capacity. The counter at the receiving station is enabled prematurely to generate the count so that the "reaction time" of the physical circuit components is compensated for. Compensation of this reaction time is important in reducing the nonlinear distortion that would otherwise be introduced when the ramp waveforms that are employed are of the companded type. The circuit operates in an overlap fashion, encoding and receiving in one field and decoding and transmitting in another field. Control time slots are interspersed between these fields and the control time slot intervals are advantageously employed to augment the code in the counter.