发明名称 |
Data processing apparatus providing variable operand width operation |
摘要 |
A Central Processing Unit provides programmable variation of the operand width for processor operations. The operands are formed with one or more N-bit segments. The CPU includes an arithmetic logic unit (ALU) which is adapted to operate serially on one N-bit segment of the operand at a time beginning with the least significant segment and repeating the operation on the remaining segments according to their order of significance. The number of repetitions of an ALU operation is controlled by a code stored in an op-code extension register (OER). The code in the OER can be changed by means of an instruction for transferring a new code to OER. |
申请公布号 |
US4258419(A) |
申请公布日期 |
1981.03.24 |
申请号 |
US19780974425 |
申请日期 |
1978.12.29 |
申请人 |
BELL TELEPHONE LABORATORIES, INCORPORATED |
发明人 |
BLAHUT, DONALD E.;COPP, DAVID H.;STANZIONE, DANIEL C. |
分类号 |
G06F9/318;G06F9/34;(IPC1-7):G06F9/34 |
主分类号 |
G06F9/318 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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