| 摘要 |
In a semiconductor memory device wherein memory cells (MC11, MC12) formed by a pair of multi-emitter transistors (TC1, TC2) each having a collector and a base which are cross connected to each other are arranged in row and column directions, and wherein read out transistors (T11, T12), each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, are arranged in each column, the patterns of the multi-emitter transistors and the patterns of the read-out transistors are such that deviations in the intended patterns of the memory cell and read-out transistors occurring during the manufacturing process tend to balance one another. This result is obtained, for example, by using a similar disposition of emitter and base electrodes, or a similar arrangement of the emitter and isolation region in multi-emitter transistors of the memory cells and in multi-emitter read-out transistors, which have different emitters connected to bit lines of different columns.
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