| 摘要 |
In an N-channel MOS integrated circuit operating in response to a major-major clock having four phases, phi 1, phi 2, phi 3 and phi 4, each of which has one, but only one, other phase which does not overlap therewith, an improved gate is disclosed wherein a first one of said phases samples an input signal for retention via a capacitive device, a second one of said phases is gated according to the state of the sample retained via the capacitive device, and a third one of said phases enhances the retention of the capacitive device.
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