| 摘要 |
PURPOSE:To obtain a J-FET of satisfactory high frequency characteristics by reducing a joint's sectional area so as to lower a gate's joining capacity, by insulating approximately half of a joint between a channel region and a semiconductor substrate occupying a major portion of the gate joining capacity. CONSTITUTION:An Si3N4 membrane 12 is attached onto the surface of a P type Si substrate 11, all the formed regions such as a source, a drain and a gate, etc. are removed, the substrate 11 is selectively turned into porous Si layers 13 and 14 by being immersed in aqueous hydrofluoric acid solution and anodized, and by being heat-treated, these layers are converted into oxide layers 15 and 16. And then, the membrane 12 is removed, an N type impurity ion is driven into the substrate exposed between the layers 15 and 16 so as to form a shallow N type layer 17, and the heights of the layers 15 and 16 are lowered by etching. And then, the surface of the projecting layer 17 is covered with an oxide membrane 18 and provided with a hole, and a source region 19 and a drain region 20 of N type are dispersingly formed on the side surface of the layer 17. And then, a P type gate region 20 is provided in the layer 17 adjoining these regions, and all the electrodes 22 through 24 of source, drain and gate are attached onto respective regions. |
