| 摘要 |
PURPOSE:To obtain the ternary counter having the output of duty 50%, by the cascade connection of flip-flops and taking the input to flip-flops with EX-OR between the clock and the output of the final stage. CONSTITUTION:The terminals P1, P2 are at ''0''. The clock pulse CP1 passes through the EX-OR gate G11 and becomes the clock pulse CP2 in-phase and the flip-flop FF11 is inverted at the leading. When the next clock pulse CP1 is fed, since FF11 is again inverted, FF12 is inverted and the output Q'12 is at ''0''. Moreover, since the next clock pulse CP1 is CP2 with inverted gate G11, FF11 is inverted at the trailing of CP1 and FF12 is inverted, allowing to obtain the ternary counter output having duty 50% at the output Q12 of FF12. By making the terminals P1, P2 as ''1'', the circuit can be used as conventional 4-notation counter. |
