| 摘要 |
PURPOSE:To enable to obtain stable return signal period through the input of counter clock from the logic circuit, by constituting the terminal monitor input of terminal unit and the return signal output section with logic circuits, in the exclusive line multiple transmission system. CONSTITUTION:When the input contact SW1 is on, the waveform differentiated at the differentiation circuit 51 is input to FF1 and counter T, FF1 is set and recorded in on-state, and the counter T is reset. When the address signal from the master unit is in agreement with the address of the terminal, while the return signal is delivered from the logic circuit 4, the address coincidence signal is counted at the counter T with the output of the gate CAG, the on-state of the input contact SW1 is returned with the 1st count output Q0, the off-state is returned with the output Q1 at the 2nd count, FF1-FF3 are reset with the output Q2 at the 3rd count, and since the output of the inverter G8 is zero, the clock input of the counter T is stopped. |
