| 摘要 |
PURPOSE:To improve synchronizing frequency precision by dividing a digital signal into high-order bits and low-order bits, by inputting the low-order bits to a low- order bit carry signal generating circuit and then by inputting the carry signal and the high-order bits to an adding circuit. CONSTITUTION:A signal from control part 14 is divided into high-order bits b4- b7 and low-order bits b0-b3. Then, low-order bits b0-b3 are supplied to gates A0-A3 of carry signal generating circuit 18 composed of a binary rate multiplier and output signals of gates A0-A3 are mixed in one to generate a carry signal. Further, the carry signal and the high-order bits are added by adder 17, the output of which is input to D/A converter 15. Thus, the number of bits of the D/A converter can be made less than that of the signal. |
