发明名称 DECIMAL MULTIPLICATION SYSTEM
摘要 PURPOSE:To reduce the overhead and attain the high speed operation by providing a construction forming a multiplication decimal multiple at the time of requisition. CONSTITUTION:The content of the multiple corresponding portion of the multiple accommodating register 12 is read by the multiple reading register 2 and then the presence or absence of the multiple is tested. If the multiple is correctly read (in the case of forming the test condition), the content enters the multiplication loop and the contents of the intermediate result accommodating register 1 and the register 2 are added by 6 and the result thereof is obtained by the register 1. Then, the value of the register 1 is shifted by 8 rightward by one column and the one shifted out column is, for example, stored as the calculation result to complete the operation of one column. In the case when the required multiple is not yet calculated, (in the case when the test condition is not established), one multiple of the multiplier is read to the register 2 and after the required multiple is obtained to the register 3 by using the work resist 3 and the decimal adding circuit 6, it enters the multiplication loop and thereafter the calculation is progressed hereinafter similarly.
申请公布号 JPS5624645(A) 申请公布日期 1981.03.09
申请号 JP19790100275 申请日期 1979.08.08
申请人 HITACHI LTD 发明人 ABE SHIYUUICHI;TAKEUCHI HIDENORI;HONMA KAZUYUKI
分类号 G06F7/52;G06F7/496;G06F7/508;G06F7/523;G06F7/527 主分类号 G06F7/52
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