发明名称 RETRIAL CONTROL SYSTEM
摘要 PURPOSE:To increase the chance of retrial to the instruction of SS type, by storing the status of instruction progress at error detection and formally executing the instruction when this stored status is in agreement with the progress information of instruction tried again. CONSTITUTION:When an error is detected, the content of the counter 1 is copied with the retrial counter 2 and stored. Simultaneously, FF4, 5 are set and the storage suppression signal from the AND circuit 6 is on. Further, the instruction counter is made by -1, and the same MOVE instruction is again fetched and executed. Further, every time the stored data is fed to the storage buffer, the content of the counter 1 is renewed, but since the storage suppression signal is on for the data in the storage buffer, it is not fed to the main memory and the data is not stored really. But, when the content of the execution counter 1 is in agreement with the content of the retrial counter 2, the storage suppression signal is off and the data is stored in the main memory actually.
申请公布号 JPS5621251(A) 申请公布日期 1981.02.27
申请号 JP19790097037 申请日期 1979.07.30
申请人 FUJITSU LTD 发明人 OINAGA YUUJI;SHIMIZU KAZUYUKI
分类号 G06F11/14 主分类号 G06F11/14
代理机构 代理人
主权项
地址