发明名称 TIMEEDIVISION SWITCH NETWORK
摘要 PURPOSE:To make it possible to increase or decrease easily the number of stages of time-division switches by assigning the selection output of the 1st-stage time switch for every time slot and then inputting it to the final-stage time switch. CONSTITUTION:At address (j) of call holding circuit PM00 of time switch TSW00, time slot information (i) is written and at address (j) of output selective control circuit SM00, gate assignment information 0 is written. On the other hand, gate assignment information 1 is written at address (j) of circuit SMO1 of switch TSW01 highway 1. Further, time slot information (j) is written at the address of circuit PM10 of switch TSW10 of highway 0. Through the above-mentioned operation, call information on time slot (i) of call signal input IS0 written at address (i) of switch TSW00 audio memory circuit MS00 is read by time slot (j) of the audio signal output of switch TSW. At this time, the audio signal output of switch TSW00 is supplied to only switch TSW. Thus, the avilability of a time switch is determined by an input time slot.
申请公布号 JPS5620396(A) 申请公布日期 1981.02.25
申请号 JP19790095891 申请日期 1979.07.26
申请人 NIPPON ELECTRIC CO 发明人 YAMAMOTO MASAHIKO
分类号 H04Q3/52;H04Q11/04 主分类号 H04Q3/52
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