| 摘要 |
PURPOSE:To reduce signal lines in number by making it possible to report error generation, by inhibiting the return of an answer signal in response to the error generation in communication between asynchronous units. CONSTITUTION:On reception of a start signal, delay circuit 2 provides fixed-time delay and then FF4 is set, sending answer signal (b). Then, FF4 is supplied with start signal (a) as a clock signal and reset at the fall of signal (a). Next, NAND circuit 3 gates the set signal of FF4 with error signal E. Therefore, once an error is generated, FF4 is never set, so tht answer signal (b) will not be sent out. |
