| 摘要 |
PURPOSE:To increase the reliability of system, by providing the spare processor to the input and output unit, storing the program required at failure in the control storage section, and reporting the failure taken place in the hardware of the main processor to the upper rank unit. CONSTITUTION:When a hardware failure is taken place at the main processor, the hardware error detector 14 detects the failure and the detection signal is delivered to the instruction execution section 8' of the spare processor and the control signal is delivered to the instruction execution section 8 to tentatively stop the control operation of the main processor. Further, the control signal from the detector 14 is delivered to the error display register 15 to display the status of the hardware failure. Further, the instruction execution section 8' reads out the microprogram at the failure stored in advance from the memory 6' and the failure status of the register 15 and the program are input to the special register 12 to execute the failure processing by taking the operation circuit 7' as a center and the failure information is transmitted to the upper rank unit via the channel interface control circuit 13. |
