发明名称 CLOCK CONTROL SYSTEM
摘要 <p>PURPOSE:To simplify the unit, by counting the start signal after generating the start signal from the access source, delivering the start signal counted at manual clock to accessed source and deleting the output data register of accessed source. CONSTITUTION:In case of manual clock providing the access source 7 and accessed source 8 and operating both sources 7, 8 synchronizingly, MEM, GO signal is held at the shift register 2. Further, immediately before the clock CLK2 from the clock delay circuit 3 requiring the read data at the control unit side is a given value, the specified value of the clock CLK1 from the oscillator 6 is fed to the access selection circuit 5 and delivered to the memory unit MEM of the accessed source 8 via the circuit 5. After that, after inputting the read data to the data register 4 of the access source 7, the data are sampled with the clock CLK2 through the circuit 3 and the switching between the manual cycle and the normal cycle is made with a simple circuit constitution.</p>
申请公布号 JPS5619126(A) 申请公布日期 1981.02.23
申请号 JP19790095325 申请日期 1979.07.26
申请人 FUJITSU LTD 发明人 YOKOMIZO SHINICHI
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
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