| 摘要 |
PURPOSE:To reduce the memory capacity of a control part while increasing a processing speed by making it possible to perform data transfer and write processing for specific codes in the same run. CONSTITUTION:To process data written in F-RAM13 and S-RAM14, the contents of designated registers in F-RAM13 and S-RAM14 are transferred to latch circuits 29 and 36 under the command of control part 11 and also input to input terminals (a) and (b) of adder circuit 22 by way of gate circuits 30 and 37. Adder circuit 22 processes the input data and the arithmetic results are written in F-RAM13 through gate 43 or in S-RAM14 through gate 45. In addition to arithmetic operation using adder circuit 22, data transfer from F-RAM13 to S-RAM14 or vice versa and the process of writing specific codes in a read-side memory can be performed in the same instruction cycle without using adder circuit 22. |
