| 摘要 |
PURPOSE:To increase a processing speed by foreseeing a shift value from a dividend and divisor and by making a shift right after deciding the shift value at the timing when an intermediate remainder is obtained. CONSTITUTION:On the basis of the contents of registers 1 and 2, arithmetic part 6 finds (A-B)>=B... CO0, (A-B)X2<=B... CO1, (A-B)X2<2>>=B... CO2, and ...(A-B)X2<n>>=B... COn simultaneously with the subtraction processing of adding circuit 3. Then, shift-value foreseeing circuit 7 determines shift value (i) satisfying 2B>(A-B)X2<i>>=B on the basis of the above-mentioned CO0, CO1, CO2.... Next, shifter 4 shifts intermediate remainder (A-B) by the above-mentioned shift value (i) immediately at the timing when intermediate remainder (A-B) is obtained and the result is set as a new intermediate remainder in register 1. |
