| 摘要 |
In order to avoid having to provide resistor ladder networks in an analogue to digital converter fabricated as an MOS integrated circuit, an array of MOS transistors (T1 to T6, T1D to T6D) are provided to form a weighted current source which draws current through a load (40) across which the analogue output voltage (VOUT) is developed. Each bit- stage of the DAC comprises an enhancement transistor (Tn) and a depletion transistor (TnD), whose source drain paths are connected in series between the load (40) and a supply rail (30), the W/L ratios of the transistors (Tn, TnD) of each stage being a factor of 2 greater or less than those of an adjacent stage. The enhancement transistor (Tn) of each stage is rendered conductive or non- conductive at will in response to an associated bit of the applied digital signal and thereby either connects or not connects the stage into the current path through the load (40). <IMAGE> |
