| 摘要 |
<p>PURPOSE:To reduce the waiting time and to speed up the data readout, by sectioning the memory element into N sets of blocks possible address designation at the same time, and reading out and latching N sets of data once at one access time. CONSTITUTION:The specified address is provided with the memory element groups 11-1, 11-2 storing the data, and the address assignment of the memory element group of the i-th sectioned into N sets of blocks is taken as the address (kN+i-1). The output of each memory group is latched to the latch circuits 13-1, 13-2 in the output timing of the timer circuit 12 and output in response to the output timing of the decoder circuit 14. Further, the upper rank bit out of the address signal line 18, is given to each memory group, addres latch circuit 15 and comparator 16, and the lower rank bit is given to the decoder circuit 14. As a result, the data k is read out succeeding to the memory data preparation end signal f.</p> |
