| 摘要 |
PURPOSE:To prevent the defective pulses from being generated, by synchronizing the frequency divided clock of opposite phase switched and selected based on the change-over command signal to the clock before division. CONSTITUTION:The clock (a) becomes the clocks (b),(c) of opposite phase frequency-divided into 1/2 or the like by the JK type FFs 1,2, and fed to the NAND gates 4,5, to which the Q,Q' outputs produced by the JK type FF3 are respectively fed in response to the change-over command pulse (d) of high and low level. Thus, the defective synchronizing pulse 2X different from the synchronism of the clocks (b),(c) is included to the clock (c) etc. switched from the clock (b) etc. of the output (e) from the OR gate 6. When this pulse (e) is processed for synchronism at the JK FF8 taking the clock (a) before the frequency division, it becomes the clock (f) without pulse X before and after the switching, allowing to prevent the production of defective pulse and to be the control pulse without malfunction. Further, the change-over command signal is synchronized with the clock before frequency division to obtain the same state. |
