| 摘要 |
PURPOSE:To quicken the operating speed of signal readout from the memory, by cascade connection of the detection circuit consisting of MISFET. CONSTITUTION:The signals at the input lines CD1, CD2 are made to opposite phase each other according to the memory information of the selected memory cell and fed to the first detection circuit consisting of MISFETQ20-Q24. The operation level of the first detection circuit is controlled with the control circuit consisting of Q25, Q26 and turned on or off with the Q44, Q45 performing switching operation according to the high or low level of signal on the control line CSX. After the output is controlled and amplified wih the 2nd detection circuit consisting of Q27-Q31 the same as the 1st detection circuit, it is fed to the 3rd detection circuit consisting of Q34-Q37 to constitute the signal where high or low level can clearly be distincted, and fed to the 4th detection circuit consisting of Q38-Q41, to obtain the readout signal at the output OUT. |
