| 摘要 |
<p>A power output circuit is provided which is protected against latching due to voltage pulses developed by an inductive load. The circuit comprises a transistor constructed on a monolithic integrated circuit chip including a grounded semiconductor substrate (102) of one (P) type conductivity, and including collector (104) and emitter (112) regions of opposite (N) type conductivity located on the substrate and containing opposite type conductivity modifiers. The collector and emitter regions are separated by a base region (110) of the one (P) type conductivity, and the collector region is coupled to the inductive load (50). A fourth region (140) of the one (P) type conductivity, containing one type conductivity modifiers is located on the substrate in galvanic contact with the collector region. A resistive impedance (40) is coupled between the fourth region (140) and a source of reference potential (ground), and a capacitor (42) is coupled between the fourth region and the source of reference potential. The capacitor (42) and the resistive impedance (40) bias the fourth localized region (140) above ground potential so that the current created by an inductively developed voltage pulse from the load (50) will be conducted to the substrate (102) by the diode junction formed by the collector (104) of the transistor and the fourth localized region (140) under these conditions. Latching of the power amplifier or supply circuitry is thereby prevented. <IMAGE></p> |
