| 摘要 |
PURPOSE:To attain correction with a required minimum delay by deciding a signal delay and a delay between 1st and 2nd time series signals and giving a decision delay to a preceding time series signal so as to apply the correction. CONSTITUTION:In receiving data A, B, frame detectors 5, 6 take frame synchronization and output frame pulses c, d respectively. The output (c) clears a counter 7 and latches the final count (a delay Y between the data B and A) of a counter 8 simultaneously to an FF 10. On the other hand, the output (d) clears the counter 8 and also latches the final count (delay X between the data A and B) of the counter 7 to an FF 9. A comparator 11 compares the delay values X, Y and in case of X<=Y, a selector 25 selects the output X of the FF 9 to bring the delay of a variable delay circuit 12 to be X. In this case, since the data A is given precedingly, the data A passes through the circuit 12 by selectors 21-24 and the data B is outputted as it is. Similarly, in case of X>Y, the data B passes through the circuit 12 and the data A is outputted as it is. |
