Semiconductor memory device including integrated injection logic memory cells.

摘要

A semiconductor integrated circuit device including integrated injektion logic (I<2>L) memory cells (Coo, Clo, ...) is disclosed. In this device, the lower of the two potentials of a selected bit line pair (Bo, Bo) is changed in response to a signal (WE) representing a command for either the read mode or the write mode, and accordingly, the difference in potential between the lines of the selected bit line pair during the read mode becomes small. With a smaller potential difference, changes in the memory state are able to be detected more rapidly by a differential read-out circuit (SAo), and accordingly the device has a high speed read operation.