| 摘要 |
A data recovery circuit is described which is suitable for use in decoding high density encoded data used in a selfclocking system, more especially where there is not a regular clock signal. The recovery circuit comprises a phase locked loop (PLL) circuit having a sample and hold phase detector (30) in combination with a voltage controlled oscillator (32) producing a ramp output. The sample and hold phase detector (30) enables the phase locked loop to track the phase of the data ("READ DATA") and to maintain a synchronized phase during bit cells when no clock pulse is present. The circuit provides for generation of a data window ("RD CLOCK") which is held in phased alignment with respect to the encoded data.
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