Synchronising circuit for clock pulse generator for message display - has pulse counter connected to generator output and receiving reset signals from reset pulse generator

摘要

The synchronising circuit, for a clock pulse generator includes a resettable pulse counter (2, 3) receiving reset signals from a reset pulse generator (35, 36) via a synchronising terminal coupled to the counter reset input (R). The circuit may be used where a standby unit is to be kept synchronised to a main unit. Pref. the pulse counter comprises a chain of resettable counters (2, 3), each with a reset input (R) supplied with reset pulses via respective synchronising terminal (27, 37). The reset pulse generator (35, 36) may have a differential input coupled to one output of the pulse counter (2, 3) and may emply a D flip-flop (25, 35) with its reset input (R) coupled to the counter input (E).