发明名称 EXTERNAL SIGNAL OFF DELAY TIMER UNIT
摘要 PURPOSE:To prevent an off-delay timer from malfunctioning in application of electric power, by resetting a counting part the output of logical operation between an external signal and the output of a flip-flop circuit reset in the application of electric power. CONSTITUTION:On feed (a) of electric power, FF5 is reset and output Q' becomes ''1'' and is supplied to reset part 4 through exclusive OR circuit 6 to let reset part 4 generate an output, resetting counting part 2. Once external signal SP is input, FF5 is set and output Q becomes ''1'', but circuit 6 outputs signal SP and while counting part 2 stays reset, output ''1'' is passed through output part 3' to generate output signal (c) of the timer. As signal SP disappears, the signal from circuit 6 becomes ''0'', and consequently counting part 2 starts counting the output of oscillation part 1 and, when reaching a preset count value, generates its output to reset FF5, making the delay output from output part 3' into ''0''.
申请公布号 JPS5612124(A) 申请公布日期 1981.02.06
申请号 JP19790088481 申请日期 1979.07.12
申请人 MATSUSHITA ELECTRIC WORKS LTD 发明人 YORIFUJI ARITAKA;YODA KENICHI
分类号 H03K17/28;H03K5/05 主分类号 H03K17/28
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