| 摘要 |
A bistable circuit and shift register requiring less chip area and with greatly reduced current drain is realized with I<s2>sL logic gates. Each cell (28) of the register includes only four logic gates (10), connected as two binary R-S flip-flops, each gate consisting of a pair of merged PNP and NPN transistors. The two flip-flops are alternately energized by switching the current into the gate injectors in accordance with the phase of the clock signal. The use of fewer gates with simplified interconnections contribute to reduce chip area and current drain. |
