| 摘要 |
PURPOSE:To obtain the competition control circuit independently of the clock, by setting FF with the first signal and the second inversion signal and setting other FF with the reset signal of FF and the second delay signal. CONSTITUTION:The signal A of read or write sets FFF5 via the AND gate G3 opened via the inverter I when the refresh signal B in competition with the signal A is absent, for the reception of the signal A. Further, the reset output of FF5 is inverted and the AND gate G4 is closed, then even if the signal B via the delay circuit DL which performs delay operation until the reset output is made stable is generated, the flip-flop F6 is not set and the signal B is not received. If the signal B is generated ahead and received, the signal A is not received, allowing to perform sure competitive control for the asynchronous signal without using clock. |
