| 摘要 |
<p>PURPOSE:To enable to obtain the circuit ease in design and less in the hardware, by combining the pulse generator generating the reference clock, counter, memory section and comparator to generate the timing train of uneven interval. CONSTITUTION:The memory section 3 writes in 3, 9, 13 at the first-third addresses respectively as the timing train of uneven interval, for example, so that the timing can be generated at the 4th, 10th, and 14th of the reference clock. The counter 2 counts the reference clock (a) of the reference clock generator 1, and the content (c) is fed to the comparator 4. The counter 5 counts the timing pulse generated as the output of the comparator 4, and the content (d) is fed to the memory section 3 as the address of the memory section 3. The comparator 4 generates the timing pulse (f) when the content (c) equals to the output (e) of the memory section 3, i.e., the clock number 3 is counted. The pulse (f) updates the content (d) of the counter 5. Thus, the memory section 3 reads out 9 and the pulse (f) is made similarly.</p> |
