发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To efficiently process the failure taken place in the buffer memory unit and to enable to log the failed part in details at the same time, by adding the ECC function to the buffer memory unit. CONSTITUTION:The ECC function is added to the buffer memory unit, and the data read out and the ECC bit are set to the data register 9 and the ECC register 9, and at the same time, the request address is set to the ECC port 14. Further, when an error is detected by the check, the production of machine check is reported to the instruction execution section, and the error information is set to the storage register 17 at the same time. Next, the corrected data are transferred to the write-in register with the data correction section 12, the address in the port 14 is moved to the execution address register 1, and the corrected data is written in the buffer memory unit. By the retrial, the content set to the registers 8 and 9 is checked and if error is detected, the effective bit of the managing information describing area of the tag section corresponding to the fixed failure is made off. After the separation designation register 18 is set, the retrial processing is received.
申请公布号 JPS5622281(A) 申请公布日期 1981.03.02
申请号 JP19790097963 申请日期 1979.07.31
申请人 FUJITSU LTD 发明人 CHIBA TAKASHI
分类号 G06F12/08;G06F13/00 主分类号 G06F12/08
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