| 摘要 |
<p>In the microcomputer and computer system field, there are arrangements, such as direct memory access circuits, which automatically generate a sequence of addresses in response to an initial address. The sequence of consecutive addresses is terminated by decrementing to zero a number representing the number of consecutive addresses required. This method for terminating the sequence requires attention of a programmer to enter the correct data for terminating the sequence of addresses. The disclosed arrangement (45, 61, 62, 99, 102) generates a sequence of addresses in response to an initial address and disables generation of the sequence of addresses in response to a control signal (LAST NIB) produced from at least a portion of the initial address at the conclusion of generation of a predetermined number of sequential addresses, the predetermined number being decoded from the initial address. </p> |
