| 摘要 |
<p>PURPOSE:To simplify the wiring and the number of clocks, and to enable the reduction of pattern size, by reading the input from external part of IC to the instruction register, through the use of period not using the data bus. CONSTITUTION:The inputs 60-63 from external IC are read to the data buses 68-71 via the transistors TR64-67. The read data is tentatively stored to the latch circuits 72-75. The outputs 76-79 of the circuits 72-75 control the instruction register and when the logic block 58 is selected, the level of the source of TR57 is output at the output 59. Further, if not selected, the source potential of TR51 is held. Further, the timings 80, 81 of precharge of this instruction register are constituted that they are in agreement with the timing 82 to read the input of external IC to the buses 68-71 or include, and this repetitive period or that inclusive only enables the input to the instruction register.</p> |
