发明名称 EQUALIZING SYSTEM OF RECEPTION ROUTE LENGTH
摘要 PURPOSE:To reduce the timing error of the frame pulse within the prescribed range for the reception routes of the two received signals of the space diversity system in the time-division multiple access communication, by giving the comparison to the frame pulses through the variable delay control circuit. CONSTITUTION:The digital signal and the synchronous signal received from routes 1 and 2 and demodulated are sent to reference synchronous signal detecting circuits 104 and 114 plus changeover switch 121 via elastic clock converters 101 and 111 and through delay circuits 103 and 113 each. And when the received signal coincides with the reference patterns of circuits 104 and 114, the output is sent to frame counters 105 and 115 each. And gate signals 138 and 147 are sent to variable delay control circuit 116 from counters 105 and 115. Thus circuit 116 gives a comparison to the timings of frame pulses 136 and 146 based on signal 138, and then the adjustment is given to the up-down counter of circuit 116. In this way, the timing error between pulses 136 and 146 can be reduced within + or -1 bit.
申请公布号 JPS5610756(A) 申请公布日期 1981.02.03
申请号 JP19790085585 申请日期 1979.07.06
申请人 NIPPON ELECTRIC CO 发明人 HOTSUTA TOSHITSUNE
分类号 H04B7/15;H04J3/00;H04L1/06 主分类号 H04B7/15
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