Multiple request arbitration circuit

摘要

Multiple usage requests for a common resource, such as a memory system, are given usage priorities by a multiple request arbitration circuit. Priority is given to a predetermined one of the input signals occurring prior to any one of the remaining input signals and priority is also given to the one input signal if it occurs within a predetermined interval subsequent to any one of the remaining input signals. The circuit also provides for the suppression of voltage transients which may occur upon the essentially simultaneous occurrence of more than one input signal and the circuit also provides a faster access time for input signals other than the predetermined one of the input signals.