| 摘要 |
PURPOSE:To enhance the working efficiency of a multiprocessor system, by providing a processor bus selecting means to each of plural data transfer memories in the multiprocessor system. CONSTITUTION:The processor bus of the #1 system when a processor bus selecting flip-flop 132 is 1. In other words, a read signal MR1 or a write signal MW1 of the #1 system, a decoder 123, a 3-state circuit 127 and a two-way driver 129 are selected and driven. Thus a reading or writing of the data becomes possible to the processor bus of the #1 system from a memory 133 and from the processor bus of the #1 system to the memory 133 respectively. On the other hand, the processor bus of the #2 system is selected when the flip-flop 132 is 0. Such memory cotrol circuit is provided to each memory to realize an independent and simultaneous transfer of data between each memory and processor bus. As a result, the queuing time is eliminated for each processor to enhance the working efficiency of a multiprocessor system. |
