TDM switching circuit with buffer memory - uses control word to switch data word through delay circuits according to weight of control bit associated with relevant delay stage

摘要

The TDM network has a circuit connecting an input time slot of an input supermultiplex way to an outgoing time slot of an output supermultiplex way. The circuit has a demultiplexer (605,90) with two outputs, one connected through a shift register delay circuit (600,601) to a second demultiplexer (605,80) the other directly to a third demultiplexer (605.80). The two outputs of each second and third demultiplexers are connected again through a shift register delay circuit and directly to two further demultiplexers respectively, and so on. An incoming information byte of eight bits is accompanied by a control word of 10 bits from an external control such as a RAM. Depending on the weight of the ninth bit of the control word the byte and the nine control word bits are switched to the selected output of the first demultiplexer. The eighth bit then determines at which output of the next demultiplexer the data byte and the remaining eight bits of the control word appear, and soon until the data bits exit the circuit through respective outputs.