Digital communications system with automatic frame synchronization and detector circuitry

摘要

Digital communication system of the type having a commutating N:1 multiplexer and a commutating 1:N demultiplexer. One of the N sources is inverted prior to being applied to the multiplexer. Automatic frame synchronization and detection circuitry is provided which repeatedly monitors the output of the demultiplexer at which the inverted signal is to appear when frame synchronization is present. Such output is monitored for signals of one logic during each monitoring time period to determine whether frame synchronization is present. A signal is obtained by such circuitry when frame synchronization is not present and is used to commutate the demultiplexer a predetermined number of steps whereby frame synchronization is attained.