发明名称 SIMULATOR FOR BIT AND BITE SYNCHRONOUS DATE NETWORK
摘要 A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals. Manual as well as automatic testing modes are provided, the manual mode including a signal stepping control arranged to enable either full or half cycle operation.
申请公布号 JPS567551(A) 申请公布日期 1981.01.26
申请号 JP19800087699 申请日期 1980.06.27
申请人 HONEYWELL INF SYSTEMS 发明人 JIEEMUZU SHII REIMONDO
分类号 H04L25/02;G06F13/00;H04L7/04;H04L12/26;H04L29/14 主分类号 H04L25/02
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