| 摘要 |
PURPOSE:To obtain a voltage step-up circuit whose output efficiency does not decrease even at low-voltage and is suitable to be employed in an integrated circuit by a method wherein two or more IGFET's, three or more complementary type inverter circuits, two or more capacitors, etc., are connected by a specified method. CONSTITUTION:At least two IGFET's 5N, 6N..., at least three complementary type inverters I1, I2, I7..., and at least two capacitors C3, C6..., etc., are connected with each others as shown in the figure. For example, a four-times voltage step-up circuit is constituted as shown in the figure. When the level of clock phi is L(-V1) in this circuit, FET's 1P, 2N, 3P, 4N, 5N, 7N, 9P, 10N, 11P are made to be ON-stage, while other FET's to be OFF-state and the electric potentials at connecting points 5-8 become respectively -V1, -3V1, -3V1, -4V1. When the level of clock phi is at H(GRD), the ON.OFF-state of FET's are made to reverse and the electric potential at the connecting point 8 remains always at -4V1. |
