| 摘要 |
PURPOSE:To obtain an integration system A/D converter with low power consumption and excellent linearity by constituting the 1st circuit by the complementary MOS FET process and constituting the 2nd circuit by the bipolar process. CONSTITUTION:A signal processing circuit 18 and an integration counter circuit 17 are integrated on one and same semiconductor substrate and power is supplied to the signal processing circuit 18 through the 1st power supply wires 31a, 31b and to the integration counter circuit 17 through the 2nd power supply wires 30a, 30b respectively. Thus, the mutual interface of the integration counter circuit 17 due to the operation of the signal processing circuit 18 is avoided, the switching jitter of pulse width signals 12a, 13a controlling current switches 12, 13 is decreased and the A/D conversion with excellent linearity is attained. Since the signal processing circuit 18 and the integration counter circuit 17 are formed by the CMOS process, the power consumption is reduced.
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